Memory-device manufacturing, memory-architecture design, and the use of memory technologies by application software all profoundly impact today’s and tomorrow’s computing systems, in terms of their performance, function, reliability, predictability, power dissipation, and cost. Existing memory technologies are seen as limiting in terms of power, capacity, and bandwidth. Emerging memory technologies offer the potential to overcome both technology- and design-related limitations to answer the requirements of many different applications. Our goal is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, to update each other on the latest state of the art, to exchange ideas, and to discuss future challenges. Please visit memsys.io for more information.

Submission Guidelines

All papers must be original and not simultaneously submitted to another journal or conference. The following paper categories are welcome:

1–2 page Abstracts

5–6 page Position Papers

10-16 page Research Papers

Conference paper format, ACM ‘sigconf’ proceedings template, blind submission (no authors listed).

List of Topics

Previously unpublished papers containing significant novel ideas and technical results are solicited. Papers that focus on system, software, and architecture level concepts specifically memory-related, i.e. topics outside of traditional conference scopes, will be preferred over others (e.g., the desired focus is away from pipeline design, processor cache design, prefetching, data prediction, etc.). Symposium topics include, but are not limited to, the following:

• Memory-system design from both hardware and software perspectives
• Memory failure modes and mitigation strategies
• Memory and system security issues
• Disaggregated Memory (e.g. CXL)
• Memory for embedded and autonomous systems (e.g., automotive)
• Operating system design for hybrid/nonvolatile memories
• Technologies including flash, DRAM, STT-MRAM, 3DXP, etc.
• Memory-centric programming models, languages, optimization
• Compute-in-memory and compute-near-memory technologies
• Data-movement issues and mitigation techniques
• Interconnects to support large-scale data movement
• Algorithmic & software memory-management techniques
• Emerging memory technologies, their controllers, and novel uses
• Interference at the memory level across datacenter applications
• Issues in the design and operation of large-memory machines
• In-memory databases and NoSQL stores
• Post-CMOS scaling efforts and memory technologies to support them, including cryogenic, neural, and heterogeneous memories
• Negative results, validation of results, invalidation of results

• To reiterate, papers that focus on topics outside the scope of traditional architecture conferences will be preferred over others.

Committees

Program Committee

• Bruce Jacob (Naval Academy)
• Abdel-Hameed Badawy (NMSU)
• Atanu Barai (LANL)
• Jonathan Beard (Google)
• Vito Giovanni Castellana (PNNL) 
• Bruce Christenson (Intel)
• Emanuele Confalonieri (Micron)
• Chen Ding (U. Rochester)
• David Donofrio (TCL)
• Ronald Dreslinski (U. Michigan)
• Wendy Elsasser (Rambus, Inc.)
• Dietmar Fey (U. Erlangen-Nuremberg)
• Maya Gokhale (LLNL)
• Simon Hammond (DoE/NNSA)
• Michael Jantz (U. Tennessee)
• Matthias Jung (U. Würzburg)
• John Leidel (TCL)
• Andres Marquez (PNNL)
• Dorin Patru (RIT)
• Ivy Bo Peng (KTH)
• Nirmal Prajapati (LANL)
• Petar Radojković (BSC)
• Marc Reichenbach (U. Rostock)
• Arun Rodrigues (SNL)
• Galen Shipman (LANL)
• Abhishek Singh (Samsung)
• Chirag Sudarshan (FZ Jülich)
• Robert Trout (Sadram)
• Thomas Vogelsang (Rambus)
• Norbert Wehn (RPTU)
• Kenneth Wright (AMD)
• Ke Zhang (ICT)

Venue

Melrose Georgetown Hotel

2430 Pennsylvania Avenue NW,Washington, DC 20037

Important Deadlines

Abstract Deadline: June 2, 2025

Submission: June 9, 2025

Notification: July 14, 2025

Camera-Ready: August 11, 2025

Conference: October 7 – October 9, 2025